Field of the Invention
The invention relates to a method and to an input circuit for evaluating a data signal at an input of a memory component.
Data signals such as those that are supplied to a memory component, for example, are subject to interference. As data transfer speeds increase, the reliability for evaluating the data signals is reduced, because even relatively slight interference has a considerable influence on the transfer of the data and can thus result in incorrect evaluating of a data item in a data signal.
Normally, a data item in a data signal is assigned to a data value by measuring a voltage level for the data signal at a particular time and assigning this voltage level to a logic data value. The particular time is generally determined by an edge of a clock signal. If interference occurs in the data signal at the time specified by the edge, an incorrect voltage level for the data signal is measured which differs from the nominal voltage level to a degree such that the measured voltage level is assigned to an incorrect logic data value.
It is accordingly an object of the invention to provide an input circuit for a memory component and a method for evaluating a data item in a data signal at an input of a memory component which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a safe method for evaluating a data signal at an input of a memory component, and to provide an input circuit for a memory component, which can be used to evaluate a data signal reliably.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for evaluating a data item in a data signal at an input of a memory component. The method includes steps of: obtaining an integration result by integrating the data signal between a start time and an end time; using a control signal to specify the start time and the end time; based on a duration of the data signal, stipulating an integration period between the start time and the end time; and based on the integration result, assigning a logic data value to the data item.
With the foregoing and other objects in view there is also provided, in accordance with the invention, an input circuit for a memory component for evaluating a data item in a data signal. The input circuit includes: a comparator device for obtaining a comparison result; an integration device for obtaining an integration value by integrating the data signal over an integration period based on a length of time that the data item is present; and a switching device for applying the data signal to the integration device. The switching device is connected to the comparator device. The comparator device obtains the comparison result by comparing the integration value with a prescribed threshold value when the integration period has elapsed and the comparator device determines a logic data value for the data item based on the comparison result.
The invention thus evaluates a data item in a data signal not at a firmly prescribed time, as in the case of evaluating methods and evaluating circuits customary to date, but rather integrates the data signal over a predetermined period during which a data item in the data signal is present. The integration reduces the influence of brief interference pulses while the data item is present. The integration result can thus be used to assign a logic data value to the data item.
The advantage of the inventive input circuit is that the data signal is integrated for a predetermined time, so that an integration value is obtained. The influence of brief interference (as compared with the duration of integration), e.g. an interference pulse, on the integration value is comparatively small, so that the inventive input circuit can be used to determine the data value of a data item reliably.
The control signal can be a validity signal that signals the presence of the data item in the data signal at the input. A validity signal is a signal which, during synchronous data transfer, indicates when a data item can be transferred or when the data signal is valid. This indication can be given in relation to a clock signal, for example. Validity signals or clock signals are frequently available at the same time as the data signal, which means that by using the validity signal as a control signal, an additional control signal does not have to be generated. This makes it possible to reduce the circuit complexity.
The integration period can depend on a period for which the data item in the data signal is present. The integration period should not exceed the period for which the data item is present. Otherwise, the data signal would be integrated over a plurality of data items, which would mean that the assignment of a logic data value to a data item were no longer possible or would require considerable complexity.
The data signal can be a double data-rate data signal in line with the double data-rate specification. The first or the second control signal is then a data strobe signal provided for transferring the double data-rate data signal. Particularly in the case of double data-rate data transfers, the high frequency used results in considerable interference that can lead to errors in the data evaluation at an input of the memory component.
Since evaluating the integration value requires that a defined initial state prevail in the integration device before the start of the integration, the integration device can be configured to start integrating the data signal at a particular initial value. To this end, the integration device can have a capacitor that is charged to a particular voltage value when the integration period has elapsed.
The input circuit can have a control input in order to start and end the integration of the data signal. This means that it is possible to use a validity signal or a clock signal available during synchronous data transfer of the data signal to generate control signals for the control input. In this way, control signals having a stipulated timing with respect to the data signal can be obtained.
The control input is preferably connected to a data strobe signal in a double data-rate transfer system. In this way, the data strobe signal controls the duration of integration. Since the data strobe signal is available anyway in a double data-rate transfer system, it is not necessary to generate an additional control signal. This allows the complexity for the input circuit to be reduced, which means that substrate area can be saved in an integrated design.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and input circuit for evaluating a data signal at an input of a memory component, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.